AMD has shared plans for the development of micro-Zen

AMD has shared plans for the development of micro-Zen

AMD has shared plans for the development of micro-Zen

A little context: Intel's top-of-the-line 28-core Xeon Skylake processor now offers about three times the floating point performance of the first-generation 32-core EPYC 7601 processor.

AMD has officially unveiled the next-generation of EPYC processors featuring the Zen 2 microarchitecture, and they look set to transform the server market once again.

One aspect of the Zen2 design has only been rumored though, but now it has been confirmed: Zen 2-based Epyc processors will use a separate I/O die.

AMD's latest "Rome" CPU features a basic chiplet design with the 7nm execution cores connected to a 14nm IO chip via faster Infinity Fabric.

One of AMD's mainstay features is socket compatibility for those that have already adopted previous generation processors. To address this Zen 2 will use CPU chiplets that house the actual computational cores, and these then connect to a single I/O die, which would handle the connection to the RAM and other devices.

Key to this better performance is AMD's choice to manufacture Rome on TSMC's 7nm process technology, which gave chip designers a larger transistor budget, while also offering increased performance and performance per watt.

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AMD is also claiming the platform's overall compute performance will be double that of its first-generation EPYC, delivering more instructions-per-cycle along with up to 400 GB/sec of memory bandwidth. When matched against a dual-socket Xeon Platinum 8180M server, the AMD box ran the benchmark to completion first.

What's not known is how much of the Rome DNA will make it into the consumer Ryzen 2 due early next year. "I am expecting improved raw core performance with frequency and IPC improvements positively impacting lower threaded workloads".

The 7nm manufacturing process and indeed the Zen timeline doesn't stop with the highly-anticipated Zen 2. If the claims hold up, the second-generation processor has a shot at being the highest performing datacenter CPU in 2019. The company's official roadmap for Ryzen 2 is 2019.

AMD is now sampling EPYC "Rome" chips with customers, with the chips expected to launch sometime in 2019.

During its Next Horizon event, AMD has also taken the opportunity to release initial information regarding its upcoming datacenter-centric Epyc processors codenamed "Rome".

AMD's multiyear investments in data center hardware and software are behind growing adoption of the company's CPUs and GPUs, said Lisa Su, AMD's president and CEO.

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